Publication

Title

A 1 GHz ADPLL with a 1.25ps Minimum-Resolution Sub-Exponent TDC in 0.18μm CMOS

Author | Seon-Kyoo Lee, Young-Hun Seo, Yunjae Suh, Hong-June Park, Jae-Yoon Sim

A 1.3μW 0.6V 8.7-ENOB Successive Approximation ADC in a 0.18μm CMOS

Author | Seon-Kyoo Lee, Seung-Jin Park, Yunjae Suh, Hong-June Park, Jae-Yoon Sim

A 650Mb/s-to-8Gb/s Referenceless CDR Circuit with Automatic Acquisition of Data Rate

Author | Seon-Kyoo Lee, Young-Sang Kim, Hyunsoo Ha, Young-Hun Seo, Hong-June Park, Jae-Yoon Sim

A Transistor-Based Background Self-Calibration for Reducing PVT Sensitivity with Design Example of an Adaptive Bandwidth PLL

Author | Seung-Jin Park, Suho Woo, Hyunsoo Ha, Yunjae Suh, Hong-June Park, Jae-Yoon Sim

A 8 GByte/s Transceiver with Current-Balanced Pseudo-Differential Signaling for Memory Interface

Author | Seon-Kyoo Lee, Dong-Woo Jee, Yunjae Suh, Hong-June Park, Jae-Yoon Sim

A Low-Voltage OP Amp with Digitally Controlled Algorithmic Approximation

Author | Dong-Woo Jee, Seung-Jin Park, Hong-June Park, Jae-Yoon Sim

A 5 Gb/s 16-bit transmitter with segmented group-inversion encoding

Author | Seon-Kyoo Lee, Yong-Sang Kim, Hong-June Park, Jae-Yoon Sim

A serpentine guard trace to reduce the far-end crosstalk induced jitter of parallel microstrip lines

Author | Kyoungho Lee, Hyun-Bae Lee, Hae-Kang Jung, Hong-June Park, Jae-Yoon Sim

A 40-to-800MHz Locking Multi-Phase DLL

Author | Young-Sang Kim, Seung-Jin Park, Yong-Sub Kim, Dong-Bi Jang, Seh-Woong Jeong, Hong-June Park, Jae-Yoon Sim

High-Speed Links for Memory Interface

Author | Jae-Yoon Sim, Seon-Kyoo Lee, Young-Sik Kim, Young-Soo Sohn, Joo Sun Choi

Charge-transferred presensing and efficiently precharged negative word-line schemes for low-voltage DRAMs

Author | Jae-Yoon Sim, Young-Gu Gang, Kyu-Nam Lim, Joong-Yong Choi, Sang-Keun Kwak, Ki-Chul Chun, Jei-Hwan Yoo, Dong-Il Seo, Soo-In Cho

A 1.0V 256Mb SDRAM with offset-compensated direct sensing and charge-recycled precharge schemes

Author | Jae-Yoon Sim, Kee-Won Kwon, Jong-Hyun Choi, Seung-Hoon Lee, Dong-Min Kim, Hyung-Ryeol Hwang, Ki-Chul Chun, Young-Hoon Seo, Hong-Sun Hwang, Dong-Il Seo, Changhyun Kim, Soo-In Cho

Double boosting pump, hybrid current sense amplifier, and binary weighted temperature sensor adjustment schemes for 1.8V 128Mb mobile DRAMs

Author | Jae-Yoon Sim, Hongil Yoon, Ki-Chul Chun, Hyun-Seok Lee, Sang-Pyo Hong, Soo-Young Kim, Min-Soo Kim, Kyu-Chan Lee, Jei-Hwan Yoo, Dong-Il Seo, Soo-In Cho

840 Mb/s CMOS demultiplexed equalizing transceiver for DRAM-to processor communication

Author | Jae-Yoon Sim, Young-Soo Sohn, Hong-June Park, Changhyun Kim, Soo-In Cho

A 1-Gb/s bidirectional I/O buffer using the current-mode scheme

Author | Jae-Yoon Sim, Hong-June Park, Soo-In Cho

Investigation of requirements for high-speed DRAM interface using Rambus-C as an example

Author | Chan-Kyung Kim, Jong-Ki Nam, Jae-Yoon Sim, Hong-June Park, Jong-Sun Kim, Soo-In Cho

A large-slew-rate fully differential folded cascode CMOS OP amp with adaptive bias

Author | Jae-Yoon Sim, Cheol-Hee Lee, Hong-June Park

A global minimum finding SPICE model parameter extraction program using the fast simulated diffusion algorithm with application to BSIM1, BSIM3, level3 and Gummel-Poon models

Author | Jae-Yoon Sim, Jong-Sun Kim, Kyung-Han Kim, Hong-June Park

A Transmitter with Different Output Timing to Compensate for the Crosstalk-Induced Jitter of Coupled Microstrip Lines

Author | Hae-Kang Jung, Soo-Min Lee, Jae-Yoon Sim, Hong-June Park

A Crosstalk-and-ISI Equalizing Receiver in 2-Drop Single-Ended SSTL Memory Channel

Author | Jun-Hyun Bae, Young-Soo Sohn, Seung-Jun Bae, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun, Jae-Yoon Sim, Hong-June Park

A Crosstalk-and-ISI Equalizing Receiver in 2-Drop Single-Ended SSTL Memory Channel

Author | Jun-Hyun Bae, Young-Soo Sohn, Seung-Jun Bae, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun, Jae-Yoon Sim, Hong-June Park

A Slew-Rate Controlled Transmitter to Compensate for the Crosstalk-Induced Jitter of Coupled Microstrip Lines

Author | Hae-Kang Jung, Soo-Min Lee, Jae-Yoon Sim, Hong-June Park

Digital Circuit of USB 2.0 PHY High Speed RX Interface

Author | Dong-Hee Yeo, Sung-Hwan Jeon, Jae-Yoon Sim, Hong-June Park

TX Digital Circuit for USB 2.0 PHY High Speed Interface

Author | Dong-Hee Yeo, Sung-Hwan Jeon, Jae-Yoon Sim, Hong-June Park

A Low-EMI 2Gbps Clock-Aligned-to-Data Intra-Panel Interface (CADI) for TFT-LCD with the VSYNC-Embedded Clock and Equalization

Author | Hyung-Joon Chi, Young-Ho Choi, Soo-Min Lee, Jae-Yoon Sim, Hong-June Park, Jongjin Lim, Pil-Sung Kang, Bu-Yeol Lee, Jin-Cheol Hong, Hee-Sub Lee

An Analytic Decision Method for the Feed-forward Equalizer Tap-Coefficients at Transmitter

Author | Soo-Min Lee, Jae-Yoon Sim, Hong-June Park

A 5-7 Gbps Peak Detector for Serial-Link

Author | Jong-Hoon Kim, Jung-Bum Shin, Jae-Yoon Sim, Hong-June Park

A 1V 2.8Gbps 0.18μm CMOS Inverter-Based Digital Differential Transmitter with Calibrations of Termination and Mismatch

Author | Jun-Hyun Bae, Sang-Hune Park, Jae-Yoon Sim, Hong-June Park

A Design Guide for 3-stage CMOS Nested Gm-C Operational Amplifier with Area or Current Minimization

Author | Jae-Seung Lee, Jae-Yoon Sim, Hong-June Park

A 4Gbps 3-bit parallel Transmitter with the Crosstalk-Induced Jitter Compensation Using TX Data Timing Control

Author | Hae-Kang Jung, Kyoungho Lee, Jong-Sam Kim, Jae-Jin Lee, Jae-Yoon Sim, Hong-June Park

A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration

Author | Hyung-Joon Chi, Jae-Seung Lee, Seong-Hwan Jeon, Seung-Jun Bae, Jae-Yoon Sim, Hong-June Park

An All-Digital 90-Degree Phase-Shift DLL with Loop-Embedded DCC for 1.6Gbps DDR Interface

Author | Jun-Hyun Bae, Jin-Ho Seo, Hwan-Seok Yeo, Jae-Whui Kim, Jae-Yoon Sim, Hong-June Park

Serpentine Guard Trace to Reduce Far-end Crosstalk and Even-Odd Mode Velocity Mismatch of Microstrip Lines by More than 40%

Author | Kyoungho Lee, Hyun-Bae Lee, Hae-Kang Jung, Jae-Yoon Sim, Hong-June Park