Research
High-speed links
The bottleneck in communication through wireline and wireless links eventually limits the system performance. Wireline transmission at tens of Gb/s through a band-limited channel causes significant loss of signal amplitude with a long tail of post-cursors, hence requiring multi-level signaling and non-trivial equalization schemes at the cost of a large power consumption. In wireless communication, a low-noise frequency generator is an essential part as it provides the carrier for the communication. Our research in this area covers developing circuits for high-speed links and phase-locked loops.
- High-speed serial/parallel links
- Clock data recovery circuits
- Phase-locked loops for 5G and beyond
- Crosstalk Cancellation for Short-Reach Interconnect
< Crosstalk Cancellation for Short-Reach Interconnect >
<Wireline Transceiver>
Injection-Locked Clock Multiplier
[VLSI 2024]
Parallel On-chip Link
[VLSI 2024]
<Selected Chip Implementations>