Publication

Title

A Low-Power Class-AB Gm-Based Amplifier With Application to an 11-bit Pipelined ADC

Author | Yunjae Suh, Seungnam Choi, and Jae-Yoon Sim

A 0.8-to-6.5 Gb/s Continuous-Rate Reference-Less Digital CDR With Half-Rate Common-Mode Clock-Embedded Signaling

Author | Kyongsu Lee, Jae-Yoon Sim

A Digitally Controlled Op-Amp with Level-Crossing-Based Approximation and its Application to a 10-bit Pipeline ADC

Author | Dong Woo Jee, Yunjae Suh, Hong-June Park, Jae-Yoon Sim

A 0.65-to-10.5 Gb/s Reference-Less CDR With Asynchronous Baud-Rate Sampling for Frequency Acquisition and Adaptive Equalization

Author | Seungnam Choi, Hyunwoo Son, Jongshin Shin, Sang-Hyun Lee, Byungsub Kim, Hong-June Park, Jae-Yoon Sim

A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC

Author | Shinwoong Kim, Seunghwan Hong, Kapseok Chang, Hyungsik Ju, Jaewook Shin, Byungsub Kim, Hong-June Park, Jae-Yoon Sim

A Coefficient-Error-Robust Feed Forward Equalizing Transmitter for Eye-variation and Power Improvement

Author | Seungho Han, Sooeun Lee, Minsoo Choi, Jae-Yoon Sim, Hong-June Park, Byungsub Kim

All-Synthesizable 5-Phase Phase-Locked Loop for USB2.0, Journal of Semiconductor Technlogy and Science

Author | Kihwan Seong, Won-Cheol Lee, Byungsub Kim, Jae-Yoon Sim, and Hong-June Park

 All-Synthesizable Current-Mode Transmitter Driver for USB2.0 interface

Author | Kihwan Seong, Won-Cheol Lee, Byungsub Kim, Jae-Yoon Sim, and Hong-June Park

A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface

Author | Soo-Min Lee, Ji-Hoon Lim, Il-Min Yi, Young-Jae Jang, Hae-Kang Jung, Kyunghoon Kim, Daehan Kwon, Byungsub Kim, Jae-Yoon Sim, Hong-June Park

A SNR-Enhanced Mutual-Capacitive Touch-Sensor ROIC Using an Averaging With Three Specific TX Frequencies, a Noise Memory, and a Compact Delay Compensation Circuit

Author | Dong-Hee Yeo, Seon-Ho Kim, Hyeon-Kyu Noh, Byungsub Kim, Jae-Yoon Sim, Hong-June Park

A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s

Author | Il-Min Yi, Soo-Min Lee, Seung-Jun Bae, Young-Soo Sohn, Jung-Hwan Choi, Seong-Jin Jang, Byungsub Kim, Jae-Yoon Sim

A Delay Locked Loop with a Feedback Edge Combiner of Duty Cycle Corrector with a 20%-80% Input-Duty-Cycle for SDRAMs

Author | Ji Hoon Lim, Jun Hyun Bae, Jaemin Jang, Hae Kang Jung, Hynbae Lee, Youngju Kim, Byungsub, Kim, Jae-Yoon Sim, Hong-June Park